EP4SE360F35I4 Datasheet, PDF (84/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

4–4
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Simplified DSP Operation
Stratix IV Simplified DSP Operation
In Stratix IV devices, the fundamental building block is a pair of 18 × 18-bit
multipliers followed by a first-stage 37-bit addition/subtraction unit, as shown in
Equation 4–1 and Figure 4–2.
1 All signed numbers, input, and output data are represented in 2’s-complement format
only.
Equation 4–1. Multiplier Equation
P[36..0] = A₀[17..0] × B₀[17..0] ± A₁[17..0] × B₁[17..0]
Figure 4–2. Basic Two-Multiplier Adder Building Block
A0[17..0]
B0[17..0]
A1[17..0]
DQ
+/-
P[36..0]
B1[17..0]
DQ
The structure shown in Figure 4–2 is useful for building more complex structures,
such as complex multipliers and 36 × 36 multipliers, as described in later sections.
Each Stratix IV DSP block contains four two-multiplier adder units (2 two-multiplier
adder units per half block). Therefore, there are eight 18 × 18 multiplier functionalities
per DSP block.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation