EP4SE360F35I4 Datasheet, PDF (76/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

3–20
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
Figure 3–16 shows sample functional waveforms of same-port read-during-write
behavior in don’t care mode for MLABs.
Figure 3–16. MLABs Same-Port Read-During Write: Don’t Care Mode
clk_a
address XX
A0
data_in _XX
wrena
FFFF
q(unregistered) XX A0(old data)
q(registered)
XX
FFFF
A1(old data)
FFFF
A1
AAAA
A2
XXXX
AAAA
A2(old data)
AAAA
For M9K and M144K memory blocks, three output choices are available in same-port
read-during-write mode: “new data” (or flow-through) or “old data”. In new data
mode, the “new data” is available on the rising edge of the same clock cycle on which
it was written. In old data mode, the RAM outputs reflect the “old data” at that
address before the write operation proceeds. In don’t care mode, the RAM outputs
“unknown values” for a read-during-write operation.
Figure 3–17 shows sample functional waveforms of same-port read-during-write
behavior in new data mode for M9K and M144K blocks.
Figure 3–17. M9K and M144K Blocks Same-Port Read-During-Write: New Data Mode
clk_a
address
rdena
wrena
bytenna
data_a
q_a (asyn)
0A
0B
01
10
00
11
A123
B456
C789
DDDD
EEEE
FFFF
XX23
B423
B423
DDDD
EEEE
FFFF
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation