EP4SE360F35I4 Datasheet, PDF (148/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–32
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
1 When using ZDB mode, to avoid signal reflection, do not place board traces on the
bi-directional I/O pin.
Figure 5–26. ZDB Mode in Stratix IV PLLs
inclk
÷n
PFD CP/LF VCO
÷C0
÷C1
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
÷m
fbout
fbin
bidirectional
I/O pin (1)
Note to Figure 5–26:
(1) The bidirectional I/O pin must be assigned to the PLL_<#>_FB_CLKOUT0p pin for left and right PLLs and to the PLL_<#>_FBp_/CLKOUT1 pin for
top and bottom PLLs.
Figure 5–27 shows an example waveform of the PLL clocks’ phase relationship in
ZDB mode.
Figure 5–27. Phase Relationship Between the PLL Clocks in ZDB Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port (1)
Dedicated PLL
Clock Outputs
Note to Figure 5–27:
(1) The internal PLL clock output can lead or lag the external PLL clock outputs.
External Feedback Mode
In external feedback mode, the external feedback input pin (fbin) is phase-aligned
with the clock input pin, as shown in Figure 5–28. Aligning these clocks allows you to
remove clock delay and skew between devices. This mode is supported on all
Stratix IV PLLs.
In external feedback mode, the output of the M counter (FBOUT) feeds back to the PLL
fbin input (using a trace on the board) becoming part of the feedback loop. Also, use
one of the dual-purpose external clock outputs as the fbin input pin in this mode.
When using external feedback mode, you must use the same I/O standard on the
input clock, feedback input, and output clocks. Left and right PLLs support this mode
when using single-ended I/O standards only.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation