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EP4SE360F35I4 Datasheet, PDF (19/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced | |||
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Chapter 1: Overview for the Stratix IV Device Family
1â5
Feature Summary
Stratix IV GT Devices
Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:
â Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA
circuitry and support data rates between 600 Mbps and 11.3 Gbps
â The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
1 The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to Table 1â7
on page 1â16.
1 For more information about Stratix IV GT devices and transceiver architecture, refer
to the Transceiver Architecture in Stratix IV Devices chapter.
Figure 1â3 shows a high-level Stratix IV GT chip view.
Figure 1â3. Stratix IV GT Chip View (1)
General Purpose
I/O and Memory
Interface
PLL PLL
PLL
General Purpose
I/O and Memory
Interface
PLL
FPGA Fabric
PLL
(Logic Elements, DSP,
PLL
PLL
Embedded Memory,
PLL
Clock Networks)
PLL
General Purpose
I/O and Memory
Interface
PLL PLL
PLL
General Purpose
I/O and Memory
Interface
Transceiver Block
600 Mbps-11.3 Gbps CDR-based Transceiver
General Purpose I/O and
High-Speed LVDS I/O
with DPA and Soft CDR
General Purpose I/O and up to 1.6 Gbps
LVDS interface with DPA and Soft-CDR
Note to Figure 1â3:
(1) Resource counts vary with device selection, package selection, or both.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1
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