EP4SE360F35I4 Datasheet, PDF (70/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

3–14
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
True Dual-Port Mode
Stratix IV M9K and M144K blocks support true dual-port mode. Sometimes called
bi-directional dual-port, this mode allows you to perform any combination of two
port operations: two reads, two writes, or one read and one write at two different
clock frequencies.
Figure 3–12 shows the true dual-port RAM configuration.
Figure 3–12. Stratix IV True Dual-Port Memory ⁽¹⁾
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
clock_a
rden_a
aclr_a
q_a[]
data_b[ ]
address_b[]
wren_b
byteena_b[]
addressstall_b
clock_b
rden_b
aclr_b
q_b[]
Note to Figure 3–12:
(1) True dual-port memory supports input/output clock mode in addition to independent clock mode.
The widest bit configuration of the M9K and M144K blocks in true dual-port mode is
as follows:
■ M9K: 512 × 16-bit (or 512 ×18-bit with parity)
■ M144K: 4K × 32-bit (or 4K ×36-bit with parity)
Wider configurations are unavailable because the number of output drivers is
equivalent to the maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, its maximum width equals half of the total
number of output drivers. Table 3–7 lists the possible M9K block mixed-port width
configurations in true dual-port mode.
Table 3–7. M9K Block Mixed-Width Configuration (True Dual-Port Mode)
Read Port
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
1K × 9
512 × 18
8K × 1
Y
Y
Y
Y
Y
—
—
4K × 2
Y
Y
Y
Y
Y
—
—
Write Port
2K × 4
Y
Y
Y
Y
Y
—
—
1K × 8
Y
Y
Y
Y
Y
—
—
512 × 16 1K × 9 512 × 18
Y
—
—
Y
—
—
Y
—
—
Y
—
—
Y
—
—
—
Y
Y
—
Y
Y
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation