EP4SE360F35I4 Datasheet, PDF (205/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–31
LVDS Input OCT (R_D)
Stratix IV devices support OCT for differential LVDS input buffers with a nominal
resistance value of 100 , as shown in Figure 6–22. Differential OCT R_D can be
enabled in row I/O banks when both the V_CCIO and V_CCPD is set to 2.5 V. Column I/O
banks do not support OCT R_D. Dedicated clock input pairs CLK[1,3,8,10][p,n],
PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of Stratix IV
devices do not support R_D termination.
Figure 6–22. Differential Input OCT
Transmitter
Receiver
Z_O = 50 Ω
Z_O = 50 Ω
100 Ω
f For more information about differential on-chip termination, refer to the High-Speed
Differential I/O Interfaces and DPA in Stratix IV Devices chapter.
Summary of OCT Assignments
Table 6–9 lists the OCT assignments for the Quartus II software version 9.1 and later.
Table 6–9. Summary of OCT Assignments in the Quartus II Software
Assignment Name
Value
Applies To
Input Termination
Parallel 50  with calibration
Differential
Input buffers for single-ended and
differential HSTL/SSTL standards
Input buffers for LVDS receivers on
row I/O banks ⁽¹⁾
Series 25  without
calibration
Output Termination
Series 50  without
calibration
Series 25  with calibration
Series 40  with calibration
Output buffers for single-ended
LVTTL/LVCMOS and HSTL/SSTL
standards as well as differential
HSTL/SSTL standards
Series 50  with calibration
Series 60  with calibration
Note to Table 6–9:
(1) You can enable differential OCT R_D in row I/O banks when both V_CCIO and V_CCPD are set to 2.5 V.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1