EP4SE360F35I4 Datasheet, PDF (302/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–22
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
Deserializer
You can statically set the deserialization factor to 3, 4, 6, 7, 8, or 10 by using the
Quartus II software. You can bypass the Stratix IV deserializer in the Quartus II
MegaWizard Plug-In Manager software to support DDR (×2) or SDR (×1) operations,
as shown Figure 8–17. The DPA and data realignment circuit cannot be used when the
deserializer is bypassed. The IOE contains two data input registers that can operate in
DDR or SDR mode.
Figure 8–17. Deserializer Bypass in Stratix IV Devices ⁽¹⁾, ⁽²⁾, ⁽³⁾
2
rx_out
FPGA
Fabric
rx_divfwdclk
rx_outclock
IOE Supports SDR, DDR, or Non-Registered Datapath
2
IOE
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
2
(LOAD_EN, diffioclk)
diffioclk
Clock Mux
LVDS Receiver
+
rx_in
Synchronizer
DOUT DIN
DPA Circuitry
Retimed ^DIN
Data
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
3 (LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
Left/Right PLL
8 Serial LVDS
Clock Phases
Notes to Figure 8–17:
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
Receiver Data Path Modes
The Stratix IV device family supports three receiver datapath modes—non-DPA
mode, DPA mode, and soft-CDR mode.
Non-DPA Mode
Figure 8–18 shows the non-DPA datapath block diagram. In non-DPA mode, the DPA
and synchronizer blocks are disabled. Input serial data is registered at the rising or
falling edge of the serial LVDS_diffioclk clock produced by the left and right PLL.
You can select the rising/falling edge option using the ALTLDVS MegaWizard
Plug-In Manager software. Both data realignment and deserializer blocks are clocked
by the LVDS_diffioclk clock, which is generated by the left and right PLL.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation