EP4SE360F35I4 Datasheet, PDF (125/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
5–9
Clock Networks in Stratix IV Devices
Clock Sources Per Quadrant
There are 26 section clock (SCLK) networks available in each spine clock that can
drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and
three core reference clocks. The SCLKs are the clock resources to the core functional
blocks, PLLs, and I/O interfaces of the device. Figure 5–9 shows that the SCLKs can
be driven by the GCLK, RCLK, PCLK, or the PLL feedback clock networks in each
spine clock.
1 A spine clock is another layer of routing below the GCLKs, RCLKs, and PCLKs before
each clock is connected to clock routing for each LAB row. The settings for spine
clocks are transparent to all users. The Quartus II software automatically routes the
spine clock based on the GCLK, RCLK, and PCLKs.
Figure 5–9. Hierarchical Clock Networks per Spine Clock ⁽¹⁾
GCLK
PLL feedback clock (4)
PCLK
RCLK
16
3
16 (2)
22 (3)
SCLK 26
9
Column I/O clock (5)
3
Core reference clock (6)
6
Row clock (7)
Notes to Figure 5–9:
(1) The GCLK, RCLK, PCLK, and PLL feedback clocks share the same routing to the SCLKs. The total number of clock
resources must not exceed the SCLK limits in each region to ensure successful design fitting in the Quartus II
software.
(2) There are up to 16 PCLKs that can drive the SCLKs in each spine clock in the largest device.
(3) There are up to 22 RCLKs that can drive the SCLKs in each spine clock in the largest device.
(4) The PLL feedback clock is the clock from the PLL that drives into the SCLKs.
(5) The column I/O clock is the clock that drives the column I/O core registers and I/O interfaces.
(6) The core reference clock is the clock that feeds into the PLL as the PLL reference clock.
(7) The row clock is the clock source to the LAB, memory blocks, and row I/O interfaces in the core row.
Clock Regions
Stratix IV devices provide up to 104 distinct clock domains (16 GCLKs + 88 RCLKs) in
the entire device. You can use these clock resources to form the following types of
clock regions:
■ Entire device
■ Regional
■ Dual-regional
To form the entire device clock region, a source (not necessarily a clock signal) drives a
GCLK network that can be routed through the entire device. This clock region has the
maximum delay when compared with other clock regions, but allows the signal to
reach every destination within the device. This is a good option for routing global
reset and clear signals or routing clocks throughout the device.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1