EP4SE360F35I4 Datasheet, PDF (262/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–38
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–14. DLL Reference Clock Input for EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin
FineLine BGA Package
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
CLK12P
DLL0
CLK13P
CLK14P
CLK1P
CLK3P
PLL_T1
PLL_L2
—
CLK15P
DLL1
CLK4P
CLK5P
CLK6P
CLK7P
CLK1P
CLK3P
PLL_B1
PLL_L3
—
DLL2
CLK4P
CLK5P
CLK6P
CLK8P
CLK10P
PLL_B2
PLL_R3
—
CLK7P
CLK12P
DLL3
CLK13P
CLK14P
CLK8P
CLK10P
PLL_T2
PLL_R2
—
CLK15P
Table 7–15. DLL Reference Clock Input for EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin FineLine
BGA Package
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
CLK12P
CLK0P
DLL0
CLK13P
CLK14P
CLK1P
CLK2P
PLL_T1
PLL_L2
—
CLK15P
CLK3P
DLL1
DLL2
CLK4P
CLK5P
CLK6P
CLK7P
CLK0P
CLK1P
CLK2P
PLL_B1
PLL_L3
—
CLK3P
CLK4P
CLK8P
CLK5P
CLK6P
CLK9P
CLK10P
PLL_B2
PLL_R3
—
CLK7P
CLK11P
CLK12P
CLK8P
DLL3
CLK13P
CLK14P
CLK9P
CLK10P
PLL_T2
PLL_R2
—
CLK15P
CLK11P
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation