EP4SE360F35I4 Datasheet, PDF (412/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

11–6
Chapter 11: SEU Mitigation in Stratix IV Devices
Error Detection Block
Error Detection Block
You can enable the Stratix IV device error detection block in the Quartus II software
(refer to “Software Support” on page 11–10). This block contains the logic necessary to
calculate the 16-bit CRC signature for the configuration CRAM bits in the device.
The CRC circuit continues running even if an error occurs. When a soft error occurs,
the device sets the CRC_ERROR pin high. Two types of CRC detection checks the
configuration bits:
■ CRAM error checking ability (16-bit CRC), which occurs during user mode to be
used by the CRC_ERROR pin.
■ For each frame of data, the pre-calculated 16-bit CRC enters the CRC circuit at
the end of the frame data and determines whether there is an error or not.
■ If an error occurs, the search engine starts to find the location of the error.
■ The error messages are shifted out through the JTAG instruction or core
interface logics while the error detection block continues running.
■ The JTAG interface reads out the 16-bit CRC result for the first frame and also
shifts the 16-bit CRC bits to the 16-bit CRC storage registers for test purposes.
■ Single error, double errors, or double-errors adjacent to each other are
deliberately introduced to configuration memory for testing and design
verification.
■ 16-bit CRC that is embedded in every configuration data frame.
■ During configuration, after a frame of data is loaded into the Stratix IV device,
the pre-computed CRC is shifted into the CRC circuitry.
■ At the same time, the CRC value for the data frame shifted-in is calculated. If
the pre-computed CRC and calculated CRC values do not match, nSTATUS is set
low. Every data frame has a 16-bit CRC; therefore, there are many 16-bit CRC
values for the whole configuration bitstream. Every device has different
lengths of configuration data frame.
1 The “Error Detection Block” section describes the 16-bit CRC only when the device is
in user mode.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation