EP4SE360F35I4 Datasheet, PDF (92/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

4–12
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
Shift registers are useful in DSP functions such as FIR filters. When implementing
18 × 18 or smaller width multipliers, you do not need external logic to create the shift
register chain because the input shift registers are internal to the DSP block. This
implementation significantly reduces the logical element (LE) resources required,
avoids routing congestion, and results in predictable timing.
The first multiplier in every half DSP block (top- and bottom-half) in Stratix IV
devices has a multiplexer for the first multiplier B-input (lower-leg input) register to
select between general routing and loopback, as shown in Figure 4–6 on page 4–9. In
loopback mode, the most significant 18-bit registered outputs are connected as
feedback to the multiplier input of the first top multiplier in each half DSP block.
Loopback modes are used by recursive filters where the previous output is needed to
compute the current output.
Loopback mode is described in “Two-Multiplier Adder Sum Mode” on page 4–22.
Table 4–3 lists input register modes for the DSP block.
Table 4–3. Input Register Modes
Register Input Mode ⁽¹⁾
9×9
12 × 12
18 × 18
36 × 36
Parallel input
Shift register input ⁽²⁾
Loopback input ⁽³⁾
Y
Y
Y
Y
—
—
Y
—
—
—
Y
—
Notes to Table 4–3:
(1) Multiplier operand input wordlengths are statically configured at compile time.
(2) Available only on the A-operand.
(3) Only one loopback input is allowed per half block. For more information, refer to Figure 4–15 on page 4–24.
Double
Y
—
—
Multiplier and First-Stage Adder
The multiplier stage natively supports 9 × 9, 12 × 12, 18 × 18, or 36 × 36 multipliers.
Other wordlengths are padded up to the nearest appropriate native wordlength; for
example, 16 × 16 would be padded up to use 18 × 18. For more information, refer to
“Independent Multiplier Modes” on page 4–15. Depending on the data width of the
multiplier, a single DSP block can perform many multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number. Two dynamic
signals, signa and signb, control the representation of each operand, respectively. A
logic 1 value on the signa/signb signal indicates that data A/data B is a signed
number; a logic 0 value indicates an unsigned number. Table 4–4 lists the sign of the
multiplication result for the various operand sign representations. The result of the
multiplication is signed if any one of the operands is a signed value.
Table 4–4. Multiplier Sign Representation
Data A (signa Value)
Data B (signb Value)
Unsigned (logic 0)
Unsigned (logic 0)
Signed (logic 1)
Signed (logic 1)
Unsigned (logic 0)
Signed (logic 1)
Unsigned (logic 0)
Signed (logic 1)
Result
Unsigned
Signed
Signed
Signed
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation