EP4SE360F35I4 Datasheet, PDF (85/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 4: DSP Blocks in Stratix IV Devices
4–5
Stratix IV Simplified DSP Operation
Following the two-multiplier adder units are the pipeline registers, the second-stage
adders, and an output register stage. You can configure the second-stage adders to
provide the alternative functions per half block, as shown in Equation 4–2 and
Equation 4–3.
Equation 4–2. Four-Multiplier Adder Equation
Z[37..0] = P₀[36..0] + P₁[36..0]
Equation 4–3. Four-Multiplier Adder Equation (44-Bit Accumulation)
W_n[43..0] = W_n-1[43..0] ± Z_n[37..0]
In these equations, n denotes sample time and P[36..0] denotes the result from the
two-multiplier adder units.
Equation 4–2 provides a sum of four 18 × 18-bit multiplication operations
(four-multiplier adder). Equation 4–3 provides a four 18 × 18-bit multiplication
operation but with a maximum 44-bit accumulation capability by feeding the output
of the unit back to itself, as shown in Figure 4–3.
Depending on the mode you select, you can bypass all register stages except
accumulation and loopback mode. In these two modes, one set of registers must be
enabled. If the register set is not enabled, an infinite loop occurs.
Figure 4–3. Four-Multiplier Adder and Accumulation Capability
Input ¹⁴⁴
Data
44
Result[]
Half-DSP Block
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1