EP4SE360F35I4 Datasheet, PDF (277/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–34 shows the delay chains in an I/O block.
Figure 7–34. Delay Chains in an I/O Block
rtena
oe
octdelaysetting1 (only)
D5 OCT
Delay
Chain
D5 Output-
Enable Delay
Chain
(outputdelaysetting1 +
outputfinedelaysetting1)
octdelaysetting2 (only)
D6 OCT
Delay
Chain
D6 Output-
Enable Delay
Chain
(outputdelaysetting2 +
outputfinedelaysetting2)
7–53
D6 Delay
Delay
Chain
D5 Delay
Delay
0
Chain
1
(outputdelaysetting2 + outputfinedelaysetting2) or
(outputonlydelaysetting2 + outputonlyfinedelaysetting2)
D1 Delay
Delay Chain
(padtoinputregisterdelaysetting +
padtoinputregisterfinedelaysetting)
Each DQS logic block contains a delay chain after the dqsbusout output and another
delay chain before the dqsenable input. Figure 7–35 shows the delay chains in the
DQS input path.
Figure 7–35. Delay Chains in the DQS Input Path
(dqsbusoutdelaysetting +
dqsbusoutfinedelaysetting)
DQS
DQS
Delay
Chain
D4 Delay
Chain
DQS
Enable
dqsin
dqsenable
dqsbusout
(dqsenabledelaysetting +
dqsenablefinedelaysetting)
T11 Delay
Chain
DQS
Enable
Control
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1