EP4SE360F35I4 Datasheet, PDF (306/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–26
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
You can use every LVDS channel in soft-CDR mode and can drive the FPGA fabric
using the periphery clock network in the Stratix IV device family. The rx_dpa_locked
signal is not valid in soft-CDR mode because the DPA continuously changes its phase
to track PPM differences between the upstream transmitter and the local receiver
input reference clocks. The parallel clock rx_outclock, generated by the left and right
PLL, is also forwarded to the FPGA fabric.
LVDS Interface with the Use External PLL Option Enabled
The ALTLVDS MegaWizard Plug-In Manager software provides an option for
implementing the LVDS interface with the Use External PLL option. With this option
enabled you can control the PLL settings, such as dynamically reconfiguring the PLL
to support different data rates, dynamic phase shift, and other settings. You also must
instantiate an ALTPLL megafunction to generate the various clock and load enable
signals.
When you enable the Use External PLL option with the ALTLVDS transmitter and
receiver, the following signals are required from the ALTPLL megafunction:
■ Serial clock input to the SERDES of the ALTLVDS transmitter and receiver
■ Load enable to the SERDES of the ALTLVDS transmitter and receiver
■ Parallel clock used to clock the transmitter FPGA fabric logic and parallel clock
used for the receiver rx_syncclock port and receiver FPGA fabric logic
■ Asynchronous PLL reset port of the ALTLVDS receiver
1 As an example, Table 8–10 describes the serial clock output, load enable output, and
parallel clock output generated on ports c0, c1, and c2, respectively, along with the
locked signal of the ALTPLL instance. You can choose any of the PLL output clock
ports to generate the interface clocks.
f With soft SERDES, a different clocking requirement is needed. For more information,
refer to the LVDS SERDES Transmitter/Receiver (ALTLVDS_RX/TX) Megafunction User
Guide.
1 The high-speed clock generated from the PLL is intended to clock the LVDS SERDES
circuitry only. Do not use the high-speed clock to drive other logic because the
allowed frequency to drive the core logic is restricted by the PLL F_OUT specification.
For more information about the F_OUT specification, refer to the DC and Switching
Characteristics for Stratix IV Devices chapter.
Table 8–10 lists the signal interface between the output ports of the ALTPLL
megafunction and the input ports of the ALTLVDS transmitter and receiver.
Table 8–10. Signal Interface Between ALTPLL and ALTLVDS_TX and ALTLVDS_RX Megafunctions (Part 1 of 2)
From the ALTPLL
Megafunction
Serial clock output (c0) ⁽¹⁾
Load enable output (c1)
To the ALTLVDS Transmitter
tx_inclock (serial clock input to the
transmitter)
tx_enable (load enable to the transmitter)
To the ALTLVDS Receiver
rx_inclock (serial clock input)
rx_enable (load enable for the
deserializer)
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation