EP4SE360F35I4 Datasheet, PDF (374/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–38
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
JTAG Configuration
Table 10–8. Dedicated Configuration Pin Connections During JTAG Configuration (Part 2 of 2)
Signal
nCONFIG
nSTATUS
CONF_DONE
DCLK
Description
Driven high by connecting to V_CCPGM, pulling up using a resistor, or driven high by
some control circuitry.
Pull to V_CCPGM using a 10-k resistor. When configuring multiple devices in the
same JTAG chain, each nSTATUS pin must be pulled up to V_CCPGM individually.
Pull to V_CCPGM using a 10-k resistor. When configuring multiple devices in the
same JTAG chain, each CONF_DONE pin must be pulled up to V_CCPGM individually.
CONF_DONE going high at the end of JTAG configuration indicates successful
configuration.
Do not leave DCLK floating. Drive low or high, whichever is more convenient on
your board.
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board
buffer.
JTAG-chain device programming is ideal when the system contains multiple devices,
or when testing your system using JTAG BST circuitry.
Figure 10–17 shows a multi-device JTAG configuration when using a download cable.
Figure 10–17. JTAG Configuration of Multiple Devices Using a Download Cable
Download Cable
10-Pin Male Header
(JTAG Mode)
V_CCPD (1)
Pin 1
(5)
V_CCPD
(1)
(1)
V_CCPD
Stratix IV Device
V_CCPGM
10 kΩ
Stratix IV Device
V_CCPGM
V_CCPGM
10 kΩ
10 kΩ
V_CCPGM
Stratix II or Stratix II GX
StratDixeIvVicDeevice
V_CCPGM
V_CCPGM
10 kΩ
10 kΩ
10 kΩ
nSTATUS
(2) _nCONFIG
CONF_DONE
(2) DCLK
nSTATUS
(2) _nCONFIG
CONF_DONE
(2) DCLK
nSTATUS
(2) _nCONFIG
CONF_DONE
(2) DCLK
(5)
(2) MSEL[2..0]
(2) MSEL[2..0]
(2) MSEL[2..0]
V_CCPD (1)
nCE (4)
V_CCPD (1)
nCE (4)
V_CCPD (1)
nCE (4)
V_IO
(3)
TRST
TDI
TMS
TDO
TCK
TRST
TDI
TMS
TDO
TCK
TRST
TDI
TMS
TDO
TCK
1 kΩ
Notes to Figure 10–17:
(1) Connect the pull-up resistor to the same supply voltage as the USB Blaster, MasterBlaster (V_IO pin), ByteBlaster II, ByteBlasterMV, or
EthernetBlaster cable. Connect the voltage supply to V_CCPD of the device.
(2) Connect the nCONFIG and MSEL[2..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect
nCONFIG to V_CCPGM and MSEL[2..0] to GND. Pull DCLK either high or low, whichever is convenient on your board.
(3) Pin 6 of the header is a V_IO reference voltage for the MasterBlaster output driver. V_IO must match the device’s V_CCPD. For more information about
this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cables,
this pin is a no connect.
(4) You must connect nCE to GND or drive it low for successful JTAG configuration.
(5) The pull-up resistor value can vary from 1 k to 10 k .
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation