EP4SE360F35I4 Datasheet, PDF (234/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–10
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–5. Number of DQS/DQ Groups per Bank in EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA
Package ⁽¹⁾, ⁽²⁾
DLL0
I/O Bank 8A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
EP4SGX290 and EP4SGX360 Devices
in the 780-Pin FineLine BGA
DLL1
I/O Bank 3A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–5:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX290 and EP4SGX360 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation