EP4SE360F35I4 Datasheet, PDF (369/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
10–33
The configuration cycle consists of three stages—reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset. To initiate
configuration in this scheme, the download cable generates a low-to-high transition
on the nCONFIG pin.
1 To begin configuration, power the V_CC, V_CCIO, V_CCPGM, and V_CCPD voltages (for the
banks where the configuration pins reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-k pull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. The programming hardware or download cable then
places the configuration data one bit at a time on the device’s DATA0 pin. The
configuration data is clocked into the target device until CONF_DONE goes high. The
CONF_DONE pin must have an external 10-k pull-up resistor for the device to initialize.
When using a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs. Additionally, the
Enable user-supplied start-up clock (CLKUSR) option has no affect on the device
initialization because this option is disabled in the .sof when programming the device
using the Quartus II programmer and download cable. Therefore, if you turn on the
CLKUSR option, you do not need to provide a clock on CLKUSR when you are
configuring the device with the Quartus II programmer and a download cable.
Figure 10–14 shows PS configuration for Stratix IV devices using a USB Blaster,
EthernetBlaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
Figure 10–14. PS Configuration Using a USB Blaster, EthernetBlaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV
Cable
V_CCPGM (1)
V_CCPGM (1)
10 kΩ
(2)
V_CCPGM (1)
10 kΩ
(2)
10 kΩ
V_CCPGM
Stratix IV Device
CONF_DONE
MSEL2
nSTATUS
MSEL1
MSEL0
V_CCPGM (1) V_CCPGM (1)
10 kΩ 10 kΩ
GND
GND
nCE
DCLK
DATA0
nCONFIG
nCEO N.C.
Download Cable
10-Pin Male Header
(PS Mode)
Pin 1
V_CCPGM (1)
GND
V_IO (3)
Shield
GND
Notes to Figure 10–14:
(1) Connect the pull-up resistor to the same supply voltage (V_CCPGM) as the USB Blaster, MasterBlaster (VIO pin), ByteBlaster II, ByteBlasterMV, or
EthernetBlaster cable.
(2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures
that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the
pull-up resistors on DATA0 and DCLK.
(3) Pin 6 of the header is a V_IO reference voltage for the MasterBlaster output driver. V_IO must match the device’s V_CCPGM. For more information about
this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cable,
this pin is a no connect.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1