EP4SE360F35I4 Datasheet, PDF (69/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
3–13
Figure 3–10 shows timing waveforms for read and write operations in simple
dual-port mode with unregistered outputs. Registering the RAM outputs simply
delays the q output by one clock cycle.
Figure 3–10. Simple Dual-Port Timing Waveforms
wrclock
wren
wraddress
data
rdclock
an-1
din-1
rden
rdaddress
bn
q (asynch) doutn-1
an
a0
din
b0
doutn
a1
a2
a3
a4
a5
a6
din4
din5
din6
b1
dout0
b2
b3
Figure 3–11 shows timing waveforms for read and write operations in mixed-port
mode with unregistered outputs.
Figure 3–11. Mixed-Port Read-During-Write Timing Waveforms
wrclock
wren
wraddress an-1
an
a0
data _din-1
din
rdclock
a1
a2
a3
a4
a5
a6
din4
din5
din6
rden
rdaddress
bn
b0
b1
b2
b3
q (asynch) doutn-1
doutn
dout0
December 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1