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EP4SE360F35I4 Datasheet, PDF (335/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced
Chapter 9: Hot Socketing and Power-On Reset in Stratix IV Devices
9–5
Power-On Reset Specifications
Power-On Reset Specifications
Table 9–1 lists the power supplies that the POR circuit monitors.
1 Altera requires powering up VCC before VCCAUX.
Table 9–1. Power Supplies Monitored by the POR Circuitry
Power Supply
VCC
VCCPT
VCCPD
VCCPGM
VCCAUX
Description
Core and periphery power supply
Programmable power technology power supply
I/O pre-driver power supply
Configuration pins power supply
Auxiliary supply for the programmable power technology
Setting (V)
0.9
1.5
2.5, 3.0
1.8, 2.5, 3.0
2.5
Table 9–2 lists the power supplies that the POR circuit does not monitor.
Table 9–2. Power Supplies Not Monitored by the POR Circuitry (Note 1)
Power Supply
Description
VCCIO
I/O power supply
VCCA_PLL
VCCD_PLL
VCC_CLKIN
PLL analog global power supply
PLL digital power supply
PLL differential clock input power supply (top and bottom I/O
banks only)
VCCBAT
Battery back-up power supply for design security volatile key
storage
Note to Table 9–2:
(1) The transceiver supplies are not monitored by POR.
Setting (V)
1.2, 1.5, 1.8,
2.5, 3.0
2.5
0.9
2.5
1.2-3.3
1 VCCIO, VCCA_PLL, VCCD_PLL, VCC_CLKIN, and VCCBAT are not monitored by POR and have
no affect on the device configuration.
The POR specification is designed to ensure that all the circuits in the Stratix IV device
are at certain known states during power up.
The POR signal pulse width is programmable using the PORSEL input pin. When the
PORSEL pin is connected to GND, the POR delay time is 100 to 300 ms. When the
PORSEL pin is set to high, the POR delay time is 4 to 12 ms.
f For more information about the POR specification, refer to the DC and Switching
Characteristics for Stratix IV Devices chapter.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1