EP4SE360F35I4 Datasheet, PDF (183/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 6: I/O Features in Stratix IV Devices
6–9
I/O Banks
Figure 6–4 through Figure 6–16 show the number of I/O pins and packaging
information for different sets of available devices. They show the top view of the
silicon die that corresponds to a reverse view for flip chip packages. They are
graphical representations only.
1 For Figure 6–4 through Figure 6–16, the pin count includes all general purpose I/Os,
dedicated clock pins, and dual purpose configuration pins. Transceiver pins and
dedicated configuration pins are not included in the pin count.
Figure 6–4. Number of I/Os in Each Bank in EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package
Number
of I/Os
Bank
Name
32 Bank 1A
26 Bank 1C
26 Bank 2C
32 Bank 2A
EP4SE230
EP4SE360
Bank 6A 32
Bank 6C 26
Bank 5C 26
Bank 5A 32
Bank
Name
Number
of I/Os
Figure 6–5. Number of I/Os in Each Bank in EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin FineLine BGA
Package
Number
of I/Os
Bank
Name
48 Bank 1A
42 Bank 1C
42 Bank 2C
48 Bank 2A
EP4SE360
EP4SE530
EP4SE820
Bank 6A 48
Bank 6C 42
Bank 5C 42
Bank 5A 48
Bank
Name
Number
of I/Os
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1