EP4SE360F35I4 Datasheet, PDF (22/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
FPGA Fabric and I/O Features
The following sections describe the Stratix IV FPGA fabric and I/O features.
Device Core Features
■ Up to 531,200 LEs in Stratix IV GX and GT devices and up to 813,050 LEs in
Stratix IV E devices, efficiently packed in unique and innovative adaptive logic
modules (ALMs)
■ Ten ALMs per logic array block (LAB) deliver faster performance, improved logic
utilization, and optimized routing
■ Programmable power technology, including a variety of process, circuit, and
architecture optimizations and innovations
■ Programmable power technology available to select power-driven compilation
options for reduced static power consumption
Embedded Memory
■ TriMatrix embedded memory architecture provides three different memory block
sizes to efficiently address the needs of diversified FPGA designs:
■ 640-bit MLAB
■ 9-Kb M9K
■ 144-Kb M144K
■ Up to 33,294 Kb of embedded memory operating at up to 600 MHz
■ Each memory block is independently configurable to be a single- or dual-port
RAM, FIFO, ROM, or shift register
Digital Signal Processing (DSP) Blocks
■ Flexible DSP blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit
full-precision multipliers at up to 600 MHz with rounding and saturation
capabilities
■ Faster operation due to fully pipelined architecture and built-in addition,
subtraction, and accumulation units to combine multiplication results
■ Optimally designed to support advanced features such as adaptive filtering, barrel
shifters, and finite and infinite impulse response (FIR and IIR) filters
Clock Networks
■ Up to 16 global clocks and 88 regional clocks optimally routed to meet the
maximum performance of 800 MHz
■ Up to 112 and 132 periphery clocks in Stratix IV GX and Stratix IV E devices,
respectively
■ Up to 66 (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in
Stratix IV GX and Stratix IV GT devices
■ Up to 71 (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in
Stratix IV E devices
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation