EP4SE360F35I4 Datasheet, PDF (71/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
3–15
Table 3–8 lists the possible M144K block mixed-port width configurations in true
dual-port mode.
Table 3–8. M144K Block Mixed-Width Configurations (True Dual-Port Mode)
Read Port
16K × 8
8K × 16
Write Port
4K × 32 16K × 9
8K × 18
16K × 8
8K × 16
4K × 32
16K × 9
8K × 18
4K × 36
Y
Y
Y
—
—
Y
Y
Y
—
—
Y
Y
Y
—
—
—
—
—
Y
Y
—
—
—
Y
Y
—
—
—
Y
Y
4K × 36
—
—
—
Y
Y
Y
In true dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output “new data” at that location or “old data”. To choose the desired
behavior, set the read-during-write behavior to either new data or old data in the
RAM MegaWizard Plug-In Manager in the Quartus II software. For more information,
refer to “Read-During-Write Behavior” on page 3–19.
In true dual-port mode, you can access any memory location at any time from either
port. When accessing the same memory location from both ports, you must avoid
possible write conflicts. A write conflict happens when you attempt to write to the
same address location from both ports at the same time. This results in unknown data
being stored to that address location. No conflict resolution circuitry is built into the
Stratix IV TriMatrix memory blocks. You must handle address conflicts external to the
RAM block.
Figure 3–13 shows true dual-port timing waveforms for the write operation at port A
and the read operation at port B, with the read-during-write behavior set to new data.
Registering the RAM’s outputs simply delays the q outputs by one clock cycle.
Figure 3–13. True Dual-Port Timing Waveform
clk_a
wren_a
address_a
data_a
q_a (asynch)
clk_b
wren_b
address_b
q_b (asynch)
an-1
din-1
an
din
din-1
a0
din
bn
doutn-1
b0
doutn
a1
dout0
a2
dout1
a3
dout2
a4
din4
dout3
a5
din5
din4
a6
din6
din5
b1
dout0
b2
dout1
b3
dout2
December 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1