EP4SE360F35I4 Datasheet, PDF (134/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–18
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
The PLL can remain locked independent of the clkena signals because the
loop-related counters are not affected. This feature is useful for applications that
require a low-power or sleep mode. The clkena signal can also disable clock outputs if
the system is not tolerant of frequency over-shoot during resynchronization.
Clock Source Control for PLLs
The clock input to Stratix IV PLLs comes from clock input multiplexers. The clock
multiplexer inputs come from dedicated clock input pins, PLLs through the GCLK
and RCLK networks, or from dedicated connections between adjacent top/bottom
and left/right PLLs. The clock input sources to top/bottom and left/right PLLs (L2,
L3, T1, T2, B1, B2, R2, and R3) are shown in Figure 5–16; the corresponding clock
input sources to left and right PLLs (L1, L4, R1, and R4) are shown in Figure 5–17.
The multiplexer select lines are only set in the configuration file (.sof or .pof). After
programmed, this block cannot be changed without loading a new configuration file
(.sof or .pof). The Quartus II software automatically sets the multiplexer select signals
depending on the clock sources selected in the design.
Figure 5–16. Clock Input Multiplexer Logic for L2, L3, T1, T2, B1, B2, R2, and R3 PLLs
clk[n+3..n] (2)
4
GCLK / RCLK input (3)
(1)
inclk0
Adjacent PLL output
To the clock
switchover block
(1)
4
inclk1
Notes to Figure 5–16:
(1) When the device is operating in user mode, input clock multiplexing is controlled through a configuration file (.sof
or .pof) only and cannot be dynamically controlled.
(2) n=0 for L2 and L3 PLLs; n=4 for B1 and B2 PLLs; n=8 for R2 and R3 PLLs, and n=12 for T1 and T2 PLLs.
(3) You can drive the GCLK or RCLK input using an output from another PLL, a pin-driven GCLK or RCLK, or through a
clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
GCLK or RCLK. An internally generated global signal or general purpose I/O pin cannot drive the PLL.
Figure 5–17. Clock Input Multiplexer Logic for L1, L4, R1, and R4 PLLs
PLL_<L1/L4/R1/R4>_CLK (1)
GCLK/RCLK (2)
4
inclk0
CLK[0..3] or CLK[8..11] (3)
inclk1
4
Notes to Figure 5–17:
(1) Dedicated clock input pins to the PLLs are L1, L4, R1, and R4, respectively. For example, PLL_L1_CLK is the
dedicated clock input for PLL_L1.
(2) You can drive the GCLK or RCLK input using an output from another PLL, a pin-driven GCLK or RCLK, or through a
clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
GCLK or RCLK. An internally generated global signal or general purpose I/O pin cannot drive the PLL.
(3) The center clock pins can feed the corner PLLs on the same side directly through a dedicated path. However, these
paths may not be fully compensated.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation