EP4SE360F35I4 Datasheet, PDF (376/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–40
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Device Configuration Pins
Figure 10–18 shows JTAG configuration of a Stratix IV device using a microprocessor.
Figure 10–18. JTAG Configuration of a Single Device Using a Microprocessor
Memory
ADDR
DATA
Microprocessor
VCCPGM ₍₁₎
VCCPGM ₍₁₎
Stratix IV Device
10 kΩ
10 kΩ
VCCPD
nSTATUS
TRST ^CONF_DONE
TDI (4)
DCLK
TCK (4) ^nCONFIG
TMS (4) ^MSEL[2..0]
TDO (4)
nCEO
(3) nCE
(2)
(2)
(2)
N.C.
GND
Notes to Figure 10–18:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain.
V_CCPGM must be high enough to meet the V_IH specification of the I/O on the device.
(2) Connect the nCONFIG and MSEL[2..0] pins to support a non-JTAG configuration scheme. If you use only a JTAG
configuration, connect nCONFIG to V_CCGPM and MSEL[2..0] to GND. Pull DCLK either high or low, whichever is
convenient on your board.
(3) Connect nCE to GND or drive it low for successful JTAG configuration.
(4) The microprocessor must use the same I/O standard as V_CCPD to drive the JTAG pins.
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or configuration
of programmable devices and testing of electronic systems, using the IEEE 1149.1
JTAG interface. Jam STAPL is a freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP
state machine.
f For more information about JTAG and Jam STAPL in embedded environments, refer
to Using Jam STAPL for ISP via an Embedded Processor. To download the Jam Player,
visit the Altera website at www.altera.com.
Device Configuration Pins
The following tables list the connections and functionality of all the
configuration-related pins on Stratix IV devices. Table 10–9 lists the Stratix IV
configuration pins and their power supply.
Table 10–9. Stratix IV Configuration Pin Summary (Part 1 of 2) (Note 1)
Description
Input/Output
Dedicated
TDI
TMS
TCK
TRST
TDO
CRC_ERROR
Input
Yes
Input
Yes
Input
Yes
Input
Yes
Output
Yes
Output
—
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V_CCPD
V_CCPD
V_CCPD
V_CCPD
V_CCPD
Pull-up
Configuration Mode
JTAG
JTAG
JTAG
JTAG
JTAG
Optional, all modes
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation