EP4SE360F35I4 Datasheet, PDF (278/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
I/O Configuration Block and DQS Configuration Block
The I/O configuration block and the DQS configuration block are shift registers that
you can use to dynamically change the settings of various device configuration bits.
The shift registers power-up low. Every I/O pin contains one I/O configuration
register, while every DQS pin contains one DQS configuration block in addition to the
I/O configuration register. Figure 7–36 shows the I/O configuration block and the
DQS configuration block circuitry.
Figure 7–36. I/O Configuration Block and DQS Configuration Block
bit 0 bit 1 bit 2
MSB
datain
update
ena
clk
Table 7–19 lists the I/O configuration block bit sequence.
Table 7–19. I/O Configuration Block Bit Sequence
Bit
Bit Name
0..3
4..6
7..10
outputdelaysetting1[0..3]
outputdelaysetting2[0..2]
padtoinputregisterdelaysetting[0..3]
Table 7–20 lists the DQS configuration block bit sequence.
Table 7–20. DQS Configuration Block Bit Sequence (Part 1 of 2)
Bit
0..3
4..6
7..10
11..14
15..18
19..22
23
24
25
26
27..29
30..33
Bit Name
dqsbusoutdelaysetting[0..3]
dqsinputphasesetting[0..2]
dqsenablectrlphasesetting[0..3]
dqsoutputphasesetting[0..3]
dqoutputphasesetting[0..3]
resyncinputphasesetting[0..3]
dividerphasesetting
enaoctcycledelaysetting
enainputcycledelaysetting
enaoutputcycledelaysetting
dqsenabledelaysetting[0..2]
octdelaysetting1[0..3]
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation