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EP4SE360F35I4 Datasheet, PDF (313/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced | |||
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
8â33
Transmitter Channel-to-Channel Skew
Transmitter channel-to-channel skew (TCCS) is an important parameter based on the
Stratix IV transmitter in a source synchronous differential interface. This parameter is
used in receiver skew margin calculation. For more information, refer to âReceiver
Skew Margin for Non-DPA Modeâ on page 8â33.
TCCS is the difference between the fastest and slowest data output transitions,
including the TCO variation and clock skew. For LVDS transmitters, the TimeQuest
Timing Analyzer provides a TCCS report, which shows TCCS values for serial output
ports.
f You can get the TCCS value from the TCCS report (report_TCCS) in the Quartus II
compilation report under the TimeQuest Timing Analyzer, or from the DC and
Switching Characteristics for Stratix IV Devices chapter.
Receiver Skew Margin for Non-DPA Mode
Changes in system environment, such as temperature, media (cable, connector, or
PCB), and loading effect the receiverâs setup and hold times; internal skew affects the
sampling ability of the receiver.
Different modes of LVDS receivers use different specifications that can help in
deciding the ability to sample the received serial data correctly. In DPA mode, you
must use DPA jitter tolerance instead of receiver input skew margin (RSKM).
In non-DPA mode, use TCCS, RSKM, and sampling window (SW) specifications for
high-speed source-synchronous differential signals in the receiver data path. The
relationship between RSKM, TCCS, and SW is expressed by the RSKM equation
shown in Equation 8â1.
Equation 8â1. RSKM
RSKM
=
-T---U-----I---â-----S---W--------â----T----C----C----S--
2
Conventions used for the equation:
â Time unit interval (TUI)âTime period of the serial data.
â RSKMâThe timing margin between the receiverâs clock input and the data input
sampling window.
â SWâThe period of time that the input data must be stable to ensure that data is
successfully sampled by the LVDS receiver. The SW is a device property and varies
with device speed grade.
â TCCSâThe timing difference between the fastest and the slowest output edges,
including tCO variation and clock skew, across channels driven by the same PLL.
The clock is included in the TCCS measurement.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1
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