EP4SE360F35I4 Datasheet, PDF (31/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
1–17
Table 1–7. Stratix IV GT Device Features (Part 2 of 2)
Feature
EP4S40G2 EP4S40G5 EP4S100G2 EP4S100G3 EP4S100G4
EP4S100G5
10G Transceiver
Channels
(600 Mbps - 11.3 Gbps
12
12
24
24
24
24
32
with PMA + PCS)
8G Transceiver
Channels
(600 Mbps - 8.5 Gbps
12
12
0
8
8
0
0
with PMA + PCS) ⁽¹⁾
PMA-only CMU
Channels
12
12
12
16
16
12
16
(600 Mbps- 6.5 Gbps)
PCIe hard IP Blocks
2
2
2
4
4
2
4
High-Speed LVDS
SERDES
46
46
46
47
47
46
47
(up to 1.6 Gbps) ⁽²⁾
SP1-4.2 Links
2
2
2
2
2
2
2
M9K Blocks
(256 x 36 bits)
1,235
1,280
1,235
936
1,248
1,280
M144K Blocks
(2048 x 72 bits)
22
64
22
36
48
64
Total Memory (MLAB +
M9K + M144K) Kb
17,133
27,376
17,133
17,248
22,564
27,376
Embedded Multipliers
18 x 18 ⁽³⁾
1,288
1,024
1,288
832
1,024
1,024
PLLs
User I/Os ⁽⁴⁾, ⁽⁵⁾
8
8
8
12
12
8
12
654
654
654
781
781
654
781
Speed Grade
(fastest to slowest)
–1, –2, –3 –1, –2, –3 –1, –2, –3 –1, –2, –3 –1, –2, –3 –1, –2, –3 –1, –2, –3
Notes to Table 1–7:
(1) You can configure all 10G transceiver channels as 8G transceiver channels. For example, the EP4S40G2F40 device has twenty-four 8G
transceiver channels and the EP4S100G5F45 device has thirty-two 8G transceiver channels.
(2) Total pairs of high-speed LVDS SERDES take the lowest channel count of R_X/T_X.
(3) Four multiplier adder mode.
(4) The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver
pins and dedicated configuration pins are not included in the pin count.
(5) This data is preliminary.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1