EP4SE360F35I4 Datasheet, PDF (133/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
5–17
Clock Enable Signals
Figure 5–14 shows how the clock enable and disable circuit of the clock control block
is implemented in Stratix IV devices.
Figure 5–14. clkena Implementation
(1)
(1)
(2)
clkena
output of clock
select mux
DQ
DQ
R1
R2
GCLK/
RCLK/
PLL_<#>_CLKOUT (1)
Notes to Figure 5–14:
(1) The R1 and R2 bypass paths are not available for the PLL external clock outputs.
(2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof).
In Stratix IV devices, the clkena signals are supported at the clock network level
instead of at the PLL output counter level. This allows you to gate off the clock even
when you are not using a PLL. You can also use the clkena signals to control the
dedicated external clocks from the PLLs. Figure 5–15 shows a waveform example for
a clock output enable. clkena is synchronous to the falling edge of the clock output.
Stratix IV devices also have an additional metastability register that aids in
asynchronous enable and disable of the GCLK and RCLK networks. You can
optionally bypass this register in the Quartus II software.
Figure 5–15. clkena Signals ⁽¹⁾
output of clock
select mux
clkena
output of AND gate
with R2 bypassed
output of AND gate
with R2 not bypassed
Note to Figure 5–15:
(1) You can use the clkena signals to enable or disable the GCLK and RCLK networks or the PLL_<#>_CLKOUT pins.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1