EP4SE360F35I4 Datasheet, PDF (343/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Passive Parallel Configuration
10–7
After power-up, the Stratix IV device goes through a POR. The POR delay depends on
the PORSEL pin setting. When PORSEL is driven low, the standard POR time is
100 ms < T_POR < 300 ms. When PORSEL is driven high, the fast POR time is
4 ms < T_POR < 12 ms. During POR, the device resets, holds nSTATUS low, and tri-states
all user I/O pins. After the device successfully exits POR, all user I/O pins continue to
be tri-stated. If nIO_pullup is driven low during power up and configuration, the user
I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are on (after
POR) before and during configuration. If nIO_pullup is driven high, the weak pull-up
resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and initialization.
While nCONFIG or nSTATUS are low, the device is in the reset stage. To initiate
configuration, the MAX II device must drive the nCONFIG pin from low to high.
1 To begin the configuration process, you must fully power V_CCPT, V_CC, V_CCPD, and
V_CCPGM of the banks where the configuration pins reside to the appropriate voltage
levels.
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-k pull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the MAX II device places
the configuration data one byte at a time on the DATA[7..0] pins.
1 A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when
the external host (a Max II CPLD or a microcontroller) is not driving the line. For
example, during external host reprogramming or power-up where the I/O driving
nCONFIG may be tri-stated. If a pull-up resistor is added to the nCONFIG line, the FPGA
stays in user mode if the external host is being reprogrammed. If a pull-down resistor
is added to the nCONFIG line, the FPGA goes into reset mode if the external host is
being reprogrammed. Whenever the nCONFIG line is released high, ensure that the first
DCLK and DATA are not driven unintentionally.
1 Stratix IV devices receive configuration data on the DATA[7..0] pins and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
If you are using the Stratix IV decompression and/or design security features,
configuration data is latched on the rising edge of every first DCLK cycle out of the four
DCLK cycles. Altera recommends that you to keep the data on DATA[7. . 0] stable for
the next 3 clock cycles when the data is being processed. You can only stop DCLK after
three clock cycles after the last data is latched.
Data is continuously clocked into the target device until CONF_DONE goes high. The
CONF_DONE pin goes high one byte early in FPP modes. The last byte is required for
FPP mode. After the device has received the next-to-last byte of the configuration data
successfully, it releases the open-drain CONF_DONE pin, which is pulled high by an
external 10-kpull-up resistor. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin. The CONF_DONE
pin must have an external 10-k pull-up resistor for the device to initialize.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1