EP4SE360F35I4 Datasheet, PDF (73/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Clocking Modes
3–17
ROM Mode
All Stratix IV TriMatrix memory blocks support ROM mode. A .mif file initializes the
ROM contents of these blocks. The address lines of the ROM are registered on M9K
and M144K blocks, but can be unregistered on MLABs. The outputs can be registered
or unregistered. Output registers can be asynchronously cleared. The ROM read
operation is identical to the read operation in the single-port RAM configuration.
FIFO Mode
All TriMatrix memory blocks support FIFO mode. MLABs are ideal for designs with
many small, shallow FIFO buffers. To implement FIFO buffers in your design, use the
Quartus II software FIFO MegaWizard Plug-In Manager. Both single- and dual-clock
(asynchronous) FIFO buffers are supported.
f For more information about implementing FIFO buffers, refer to the SCFIFO and
DCFIFO Megafunctions User Guide.
1 MLABs do not support mixed-width FIFO mode.
Clocking Modes
Stratix IV TriMatrix memory blocks support the following clocking modes:
■ “Independent Clock Mode” on page 3–18
■ “Input/Output Clock Mode” on page 3–18
■ “Read/Write Clock Mode” on page 3–18
■ “Single Clock Mode” on page 3–18
c Violating the setup or hold time on the memory block address registers could corrupt
memory contents. This applies to both read and write operations.
Table 3–9 lists which clocking mode/memory mode combinations are supported.
Table 3–9. TriMatrix Memory Clock Modes
Clocking Mode
True
Dual-Port Mode
Independent
Y
Input/output
Y
Read/write
—
Single clock
Y
Simple
Dual-Port Mode
—
Y
Y
Y
Single-Port Mode
—
Y
—
Y
ROM Mode
Y
Y
—
Y
FIFO Mode
—
—
Y
Y
December 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1