EP4SE360F35I4 Datasheet, PDF (175/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

September 2012
SIV51006-3.4
SIV51006-3.4
6. I/O Features in Stratix IV Devices
This chapter describes how Stratix^ IV devices provide I/O capabilities that allow
you to work in compliance with current and emerging I/O standards and
requirements. With these device features, you can reduce board design interface costs
and increase development flexibility.
Altera^ Stratix IV FPGAs deliver a breakthrough level of system bandwidth and
power efficiency for high-end applications, allowing you to innovate without
compromise. Stratix IV I/Os are specifically designed for ease-of-use and rapid
system integration while simultaneously providing the high bandwidth required to
maximize internal logic capabilities and produce system-level performance.
Stratix IV device I/O capability far exceeds the I/O bandwidth available from
previous generation FPGAs. Independent modular I/O banks with a common bank
structure for vertical migration lend efficiency and flexibility to the high-speed I/O.
Package and die enhancements with dynamic termination and output control provide
best-in-class signal integrity. Numerous I/O features assist high-speed data transfer
into and out of the device, including:
■ Up to 32 full-duplex clock data recovery (CDR)-based transceivers supporting
data rates between 600 Mbps and 8.5 Gbps
■ Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express^® (PIPE) (PCIe) Gen1 and Gen2, Gigabit Ethernet
(GbE), Serial RapidIO^®, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G,
SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken
■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that
implement PHY-MAC layer, data link layer, and transaction layer functionality
■ Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
■ Low-voltage differential signaling (LVDS), reduced swing differential signaling
(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTL
■ Single data rate (SDR) and half data rate (HDR—half frequency and twice data
width of SDR) input and output options
■ Up to 132 full duplex 1.6 Gbps true LVDS channels (132 Tx + 132 Rx) on the row
I/O banks
■ Hard dynamic phase alignment (DPA) block with serializer/deserializer
(SERDES)
■ Deskew, read and write leveling, and clock-domain crossing functionality
■ Programmable output current strength
■ Programmable slew rate
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Stratix IV Device Handbook
Volume 1
September 2012
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