EP4SE360F35I4 Datasheet, PDF (249/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–25
1 The parity, DM, BWSn, NWSn, ECC, and QVLD pins are shown as DQ pins in the pin
table.
The numbering scheme starts from the top-left corner of the device going
counter-clockwise in a die-top view. Figure 7–20 shows how the DQS/DQ groups are
numbered in a die-top view of the device. The top and bottom sides of the device can
contain up to 38 ×4 DQS/DQ groups. The left and right sides of the device can contain
up to 34 ×4 DQS/DQ groups.
Figure 7–20. DQS Pins in Stratix IV I/O Banks
DQS38T
DQS20T
DQS19T
DQS1T
DLL0
PLL_T1 PLL_T2
DLL3
PLL_L1
8A
8B
8C
7C
7B
7A
PLL_R1
DQS1L
DQS34R
1A
6A
1B
6B
1C
DQS17L
PLL_L2
PLL_L3
DQS18L
2C
Stratix IV Device
6C
DQS18R
PLL_R2
PLL_R3
DQS17R
5C
2B
5B
2A
5A
DQS34L
DQS1R
PLL_L4
3A
3B
3C
4C
4B
4A
PLL_R4
PLL_B1 PLL_B2
DLL1
DLL2
DQS1B
DQS19B
DQS20B
DQS38B
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1