EP4SE360F35I4 Datasheet, PDF (40/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

2–4
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Logic Array Blocks
LAB Interconnects
The LAB local interconnect can drive ALMs in the same LAB. It is driven by column
and row interconnects and ALM outputs in the same LAB. Neighboring
LABs/MLABs, M9K RAM blocks, M144K blocks, or digital signal processing (DSP)
blocks from the left or right can also drive the LAB’s local interconnect through the
direct link connection. The direct link connection feature minimizes the use of row
and column interconnects, providing higher performance and flexibility. Each LAB
can drive 30 ALMs through fast-local and direct-link interconnects.
Figure 2–3 shows the direct-link connection.
Figure 2–3. Direct-Link Connection
Direct-link interconnect from the
left LAB, TriMatrix memory
block, DSP block, or IOE output
Direct-link interconnect from the
right LAB, TriMatrix memory
block, DSP block, or IOE output
ALMs
ALMs
Direct-link
interconnect
to left
Local
Interconnect
Direct-link
interconnect
to right
MLAB
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs. Control
signals include three clocks, three clock enables, two asynchronous clears, a
synchronous clear, and synchronous load control signals. This gives a maximum of 10
control signals at a time. Although you generally use synchronous-load and clear
signals when implementing counters, you can also use them with other functions.
Each LAB has two unique clock sources and three clock enable signals, as shown in
Figure 2–4. The LAB control block can generate up to three clocks using two clock
sources and three clock enable signals. Each LAB’s clock and clock enable signals are
linked. For example, any ALM in a particular LAB using the labclk1 signal also uses
the labclkena1 signal. If the LAB uses both the rising and falling edges of a clock, it
also uses two LAB-wide clock signals. De-asserting the clock enable signal turns off
the corresponding LAB-wide clock.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation