EP4SE360F35I4 Datasheet, PDF (138/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–22
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Figure 5–18 shows the location of PLLs in Stratix IV devices.
Figure 5–18. PLL Locations in Stratix IV Devices
Top/Bottom PLLs
Top/Bottom PLLs
CLK[12..15]
T1 T2
PLL_L1_CLK L1
R1 PLL_R1_CLK
Left/Right PLLs
Left/Right PLLs
L2
CLK[0..3]
L3
Q1 Q2
Q4 Q3
R2
CLK[8..11]
R3
Left/Right PLLs
Left/Right PLLs
PLL_L4_CLK ^L4
B1 B2
CLK[4..7]
Top/Bottom PLLs
Top/Bottom PLLs
R4 PLL-R4_CLK
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation