EP4SE360F35I4 Datasheet, PDF (43/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
Figure 2–6 shows a detailed view of all the connections in an ALM.
Figure 2–6. Stratix IV ALM Connection Details
dataf0
datae0
dataa
datab
datac0
shared_arith_in
carry_in
4-INPUT
LUT
syncload
aclr[1:0]
clk[2:0] sclr
reg_chain_in
GND
+
3-INPUT
LUT
CLR
D
Q
3-INPUT
LUT
2–7
local
interconnect
row, column
direct link routing
row, column
direct link routing
datac1
datae1
dataf1
4-INPUT
LUT
3-INPUT
LUT
3-INPUT
LUT
+
VCC
CLR
D
Q
local
interconnect
row, column
direct link routing
row, column
direct link routing
shared_arith_out
carry_out
reg_chain_out
One ALM contains two programmable registers. Each register has data, clock, clock
enable, synchronous and asynchronous clear, and synchronous load and clear inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive the register’s
clock and clear-control signals. Either general-purpose I/O pins or internal logic can
drive the clock enable. For combinational functions, the register is bypassed and the
output of the LUT drives directly to the outputs of an ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register outputs can drive these output drivers (refer to
Figure 2–6). For each set of output drivers, two ALM outputs can drive column, row,
or direct-link routing connections. One of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output while the
register drives another output.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1