EP4SE360F35I4 Datasheet, PDF (162/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–46
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Table 5–10 lists how these signals can be driven by the PLD logic array or I/O pins.
Table 5–10. Real-Time PLL Reconfiguration Ports
PLL Port Name
scandata
scanclk
scanclkena
configupdate
scandone
scandataout
Description
Source
Serial input data stream to scan
chain.
Logic array or I/O pin
Serial clock input signal. This clock
can be free running.
GCLK, RCLK or I/O pins
Enables scanclk and allows the
scandata to be loaded in the scan
chain. Active high.
Logic array or I/O pin
Writes the data in the scan chain to
the PLL. Active high.
Logic array or I/O pin
Indicates when the PLL has finished
reprogramming. A rising edge
indicates the PLL has begun
reprogramming. A falling edge
indicates the PLL has finished
reprogramming.
PLL reconfiguration circuit
Used to output the contents of the
scan chain.
PLL reconfiguration circuit
Destination
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
Logic array or I/O pins
Logic array or I/O pins
To reconfigure the PLL counters, follow these steps:
1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in the
first bit of scandata (D0).
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
scanclk.
3. After all 234 bits (top and bottom PLLs) or 180 bits (left and right PLLs) have been
scanned into the scan chain, the scanclkena signal is de-asserted to prevent
inadvertent shifting of bits in the scan chain.
4. The configupdate signal is asserted for one scanclk cycle to update the PLL
counters with the contents of the scan chain.
5. The scandone signal goes high, indicating the PLL is being reconfigured. A falling
edge indicates the PLL counters have been updated with new settings.
6. Reset the PLL using the areset signal if you make any changes to the M, N, or
post-scale output C counters or to the Icp, R, or C settings.
7. You can repeat steps 1-5 to reconfigure the PLL any number of times.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation