EP4SE360F35I4 Datasheet, PDF (115/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 4: DSP Blocks in Stratix IV Devices
Software Support
4–35
Table 4–9. DSP Block Dynamic Signals (Part 2 of 2)
Signal Name
accum_sload
zero_chainout
zero_loopback
rotate
shift_right
Total Signals per Half Block
Function
Dynamically specifies whether the accumulator value is zero.
■ accum_sload = 0, accumulation input is from the output registers
■ accum_sload = 1, accumulation input is set to zero
Dynamically specifies whether the chainout value is zero.
Dynamically specifies whether the loopback value is zero.
rotate = 1, the rotation feature is enabled
shift_right = 1, the shift right feature is enabled
clock0
clock1
clock2
DSP-block-wide clock signals.
clock3
ena0
ena1
ena2
Input and Pipeline Register enable signals.
ena3
aclr0
aclr1
aclr2
DSP block-wide asynchronous clear signals (active low).
aclr3
Total Count per Full Block
Count
1
1
1
1
1
11
4
4
4
34
Software Support
Altera provides two distinct methods for implementing various modes of the DSP
block in a design—instantiation and inference. Both methods use the following
Quartus II megafunctions:
■ lpm_mult
■ altmult_add
■ altmult_accum
■ altfp_mult
To use the DSP block, instantiate the megafunctions in the Quartus II software.
Alternatively, with inference, create an HDL design and synthesize it using a
third-party synthesis tool (such as LeonardoSpectrum, Synplify, or Quartus II
Native Synthesis) that infers the appropriate megafunction by recognizing
multipliers, multiplier adders, multiplier accumulators, and shift functions. Using
either method, the Quartus II software maps the functionality to the DSP blocks
during compilation.
f For instructions about using these megafunctions and the MegaWizard Plug-In
Manager, refer to Quartus II software Help.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1