EP4SE360F35I4 Datasheet, PDF (229/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
7–5
Memory Interfaces Pin Support
The DQS and DQ pin locations are fixed in the pin table. Memory interface circuitry is
available in every Stratix IV I/O bank that does not support transceivers. All the
memory interface pins support the I/O standards required to support DDR3, DDR2,
DDR SDRAM, QDR II+, QDR II SRAM, and RLDRAM II devices.
The Stratix IV device family supports DQS and DQ signals with DQ bus modes of ×4,
×8/×9, ×16/×18, or ×32/×36, although not all devices support DQS bus mode
×32/×36. When any of these pins are not used for memory interfacing, you can use
them as user I/Os. In addition, you can use any DQSn or CQn pins not used for
clocking as DQ (data) pins. Table 7–1 lists pin support per DQS/DQ bus mode,
including the DQS/CQ and DQSn/CQn pin pair.
Table 7–1. Stratix IV DQS/DQ Bus Mode Pins
Mode
DQSn Support
CQn Support
Parity or DM
QVLD
(Optional) (Optional) ⁽¹⁾
Typical
Number of
Data Pins
per Group
Maximum
Number of
Data Pins
per Group ⁽²⁾
×4
Yes
×8/×9 ⁽³⁾
Yes
×16/×18 ⁽⁴⁾
Yes
×32/×36 ⁽⁵⁾
Yes
×32/×36 ⁽⁷⁾
Yes
No
No ⁽⁶⁾
No
4
5
Yes
Yes
Yes
8 or 9
11
Yes
Yes
Yes
16 or 18
23
Yes
Yes
Yes
32 or 36
47
Yes
No ⁽⁸⁾
Yes
32 or 36
39
Notes to Table 7–1:
(1) The QVLD pin is not used in the ALTMEMPHY megafunction.
(2) This represents the maximum number of DQ pins (including parity, data mask, and QVLD pins) connected to the DQS bus network with
single-ended DQS signaling. When you use differential or complementary DQS signaling, the maximum number of data per group decreases
by one. This number may vary per DQS/DQ group in a particular device. Check the pin table for the exact number per group. For DDR3, DDR2,
and DDR interfaces, the number of pins is further reduced for an interface larger than ×8 due to the need of one DQS pin for each ×8/×9 group
that is used to form the x16/×18 and ×32/×36 groups.
(3) Two ×4 DQS/DQ groups are stitched to make a ×8/×9 group so there are a total of 12 pins in this group.
(4) Four ×4 DQS/DQ groups are stitched to make a ×16/×18 group.
(5) Eight ×4 DQS/DQ groups are stitched to make a ×32/×36 group.
(6) The DM pin can be supported if differential DQS is not used and the group does not have additional signals.
(7) These ×32/×36 DQS/DQ groups are available in EP4SGX290, EP4SGX360, and EP4SGX530 devices in 1152- and 1517-pin FineLine BGA
packages. There are 40 pins in each of these DQS/DQ groups.
(8) There are 40 pins in each of these DQS/DQ groups. The BWSn pins cannot be placed within the same DQS/DQ group as the write data pins
because of insufficient pins available.
Table 7–2 lists the number of DQS/DQ groups available per side in each Stratix IV
device. For a more detailed listing of the number of DQS/DQ groups available per
bank in each Stratix IV device, see Figure 7–3 through Figure 7–19. These figures
represent the die-top view of the Stratix IV device.
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 1 of 3) ⁽¹⁾
Device
Package
Side
×4 ⁽²⁾
×8/×9
×16/×18
EP4SGX70
Left
14
6
2
EP4SGX110
780-pin
Top/Bottom
17
8
2
EP4SGX180
FineLine BGA
EP4SGX230
Right
0
0
0
EP4SGX290
780-pin
Left/Right
0
0
0
EP4SGX360
FineLine BGA
Top/Bottom
18
8
2
×32/×36 ⁽³⁾
0
0
0
0
0
Refer to:
Figure 7–3
Figure 7–5
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1