EP4SE360F35I4 Datasheet, PDF (293/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
8–13
Figure 8–6 shows the Stratix IV transmitter in clock output mode. In clock output
mode, you can use an LVDS channel as a clock output channel.
Figure 8–6. Stratix IV Transmitter in Clock Output Mode
Transmitter Circuit
Parallel
Series
FPGA
Fabric
Txclkout+
Txclkout–
Left/Right
PLL
diffioclk
LVDS_LOAD_EN
You can bypass the Stratix IV serializer to support DDR (×2) and SDR (×1) operations
to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE)
contains two data output registers that can each operate in either DDR or SDR mode.
Figure 8–7 shows the serializer bypass path.
Figure 8–7. Serializer Bypass in Stratix IV Devices ⁽¹⁾, ⁽²⁾, ⁽³⁾
tx_in ₂
FPGA
Fabric
Serializer 2
IOE
DIN DOUT
tx_coreclock
3
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
Left/Right PLL
IOE supports SDR, DDR, or
Non-Registered Datapath
LVDS Transmitter
tx_out
+
-
Notes to Figure 8–7:
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width to the IOE is 1 and 2 bits, respectively.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1