EP4SE360F35I4 Datasheet, PDF (303/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
8–23
1 When using non-DPA receivers, you must drive the PLL from a dedicated and
compensated clock input pin. Compensated clock inputs are dedicated clock pins in
the same I/O bank as the PLL.
f For more information about dedicated and compensated clock inputs, refer to the
Clock Networks and PLLs in Stratix IV Devices chapter.
Figure 8–18. Receiver Data Path in Non-DPA Mode ⁽¹⁾, ⁽²⁾
10
rx_out
IOE Supports SDR, DDR, or Non-Registered Datapath
2
IOE
FPGA
Fabric
rx_divfwdclk
rx_outclock
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
2
(LOAD_EN, diffioclk)
diffioclk
Clock Mux
LVDS Receiver
+
rx_in
Synchronizer
DOUT DIN
DPA Circuitry
Retimed _DIN
Data
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
3 _{(LVDS_LOAD_EN,}
LVDS_diffioclk,
rx_outclk)
Left/Right PLL
rx_inclock
Notes to Figure 8–18:
(1) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(2) The rx_out port has a maximum data width of 10 bits.
8 Serial LVDS
Clock Phases
LVDS Clock Domain
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1