EP4SE360F35I4 Datasheet, PDF (283/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
8–3
Locations of the I/O Banks
The ALTLVDS transmitter and receiver requires various clock and load enable signals
from a left or right PLL. The Quartus^® II software provides the following two choices
when configuring the LVDS SERDES circuitry when using the PLL:
■ LVDS interface with the Use External PLL option enabled—You control the PLL
settings, such as dynamically reconfiguring the PLL to support different data
rates, dynamic phase shift, and so on. You must enable the Use External PLL
option in the ALTLVDS_TX and ALTLVDS_RX megafunctions, using the
ALTLVDS MegaWizard^ Plug-in Manager software. You also must instantiate an
ALTPLL megafunction to generate the various clocks and load enable signals. For
more information, refer to “LVDS Interface with the Use External PLL Option
Enabled” on page 8–26.
■ LVDS interface with the Use External PLL option disabled—The Quartus II
software configures the PLL settings automatically. The software is also
responsible for generating the various clock and load enable signals based on the
input reference clock and data rate selected.
1 Both choices target the same physical PLL; the only difference is the additional
flexibility provided when an LVDS interface has the Use External PLL option enabled.
Locations of the I/O Banks
Stratix IV I/Os are divided into 16 to 24 I/O banks. The dedicated circuitry that
supports high-speed differential I/Os is located in banks in the right and left side of
the device. Figure 8–2 shows a high-level chip overview of the Stratix IV E device.
Figure 8–2. High-Speed Differential I/Os with DPA Locations in Stratix IV E Devices
General Purpose
I/O and Memory
Interface
PLL
PLL PLL
General Purpose
I/O and Memory
Interface
PLL
FPGA Fabric
PLL
(Logic Elements, DSP,
PLL
PLL
Embedded Memory,
PLL
Clock Networks)
PLL
General Purpose
I/O and Memory
Interface
PLL PLL
PLL
General Purpose
I/O and Memory
Interface
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1