EP4SE360F35I4 Datasheet, PDF (129/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
5–13
1 Dedicated clock pins can drive PLLs over dedicated routing; they do not require the
global or regional network. Compensated inputs, which are a subset of dedicated
clock pins, drive PLLs that can only compensate the input delay when a dedicated
clock pin is in the same I/O bank as the PLL used.
Clock Output Connections
PLLs in Stratix IV devices can drive up to 20 RCLK networks and four GCLK
networks. For Stratix IV PLL connectivity to GCLK networks, refer to Table 5–5. The
Quartus II software automatically assigns PLL clock outputs to RCLK and GCLK
networks.
Table 5–5 lists how the PLL clock outputs connect to the GCLK networks.
Table 5–5. Stratix IV PLL Connectivity to the GCLK Networks ⁽¹⁾
Clock Network
PLL Number
L1 L2 L3 L4 B1 B2 R1 R2 R3 R4 T1 T2
GCLK0
Y Y Y Y ————————
GCLK1
Y Y Y Y ————————
GCLK2
Y Y Y Y ————————
GCLK3
Y Y Y Y ————————
GCLK4
———— Y Y ——————
GCLK5
———— Y Y ——————
GCLK6
———— Y Y ——————
GCLK7
———— Y Y ——————
GCLK8
—————— Y Y Y Y ——
GCLK9
—————— Y Y Y Y ——
GCLK10
—————— Y Y Y Y ——
GCLK11
—————— Y Y Y Y ——
GCLK12
—————————— Y Y
GCLK13
—————————— Y Y
GCLK14
—————————— Y Y
GCLK15
—————————— Y Y
Note to Table 5–5:
(1) Only PLL counter outputs C0 - C3 can drive the GCLK networks.
Table 5–6 lists how the PLL clock outputs connect to the RCLK networks.
Table 5–6. Stratix IV RCLK Outputs From the PLL Clock Outputs ⁽¹⁾ (Part 1 of 2)
PLL Number
Clock Resource
L1 L2 L3 L4 B1 B2 R1 R2 R3 R4 T1 T2
RCLK[0..11]
— Y Y — — — — — ——— —
RCLK[12..31] — — — — Y Y — — — — — —
RCLK[32..43] — — — — — — — Y Y — — —
RCLK[44..63] — — — — — — — — — — Y Y
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1