EP4SE360F35I4 Datasheet, PDF (362/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–26
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
PS Configuration Using a MAX II Device as an External Host
In this configuration scheme, you can use a MAX II device as an intelligent host that
controls the transfer of configuration data from a storage device, such as flash
memory, to the target Stratix IV device. You can store configuration data in .rbf, .hex,
or .ttf format.
Figure 10–10 shows the configuration interface connections between a Stratix IV
device and a MAX II device for single device configuration.
Figure 10–10. Single Device PS Configuration Using an External Host
Memory
ADDR
DATA0
V_{CCPGM (1)} V_{CCPGM (1) VCCPGM/VCCIO (2)}
10 k Ω 10 k Ω
10 kΩ
Stratix IV Device
External Host
(MAX II Device or
Microprocessor)
GND
CONF_DONE
nSTATUS
nCE
nCEO
DATA0
nCONFIG
DCLK
MSEL2
MSEL1
MSEL0
N.C.
V_CCPGM
GND
Note to Figure 10–10:
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix IV device. V_CCPGM must be
high enough to meet the V_IH specification of the I/O on the device and the external host. Altera recommends powering
up all configuration system I/Os with V_CCPGM.
(2) A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when the external host is not driving
the line.
After power-up, Stratix IV devices go through a POR. The POR delay depends on the
PORSEL pin setting. When PORSEL is driven low, the standard POR time is
100 ms < T_POR < 300 ms. When PORSEL is driven high, the fast POR time is
4 ms < T_POR < 12 ms. During POR, the device resets, holds nSTATUS low, and tri-states
all user I/O pins. After the device successfully exits POR, all user I/O pins continue to
be tri-stated. If nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins will have weak pull-up resistors that are on
(after POR) before and during configuration. If nIO_pullup is driven high, the weak
pull-up resistors are disabled.
The configuration cycle consists of three stages—reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset. To initiate
configuration, the MAX II device must generate a low-to-high transition on the
nCONFIG pin.
1 V_CC, V_CCIO, V_CCPGM, and V_CCPD of the banks where the configuration pins reside must
be fully powered to the appropriate voltage levels to begin the configuration process.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation