EP4SE360F35I4 Datasheet, PDF (62/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

3–6
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
Address Clock Enable Support
All Stratix IV memory blocks support address clock enable, which holds the previous
address value for as long as the signal is enabled (addressstall = 1). When the
memory blocks are configured in dual-port mode, each port has its own independent
address clock enable. The default value for the address clock enable signals is low
(disabled).
Figure 3–2 shows an address clock enable block diagram. The address clock enable is
referred to by the port name addressstall.
Figure 3–2. Address Clock Enable
address[0]
1
address[0]
0
register
address[0]
address[N]
addressstall
clock
1
address[N]
0
register
address[N]
Figure 3–3 shows the address clock enable waveform during the read cycle.
Figure 3–3. Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
a0
a1
a2
rden
addressstall
latched address
(inside memory) ^an
a0
q (synch) doutn-1 doutn
dout0
q (asynch) doutn
dout0
a3
a4
a1
dout1
dout1
a5
a6
a4
a5
dout4
dout4
dout5
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation