EP4SE360F35I4 Datasheet, PDF (64/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

3–8
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
Error Correction Code (ECC) Support
Stratix IV M144K blocks have built-in support for error correction code (ECC) when in
×64-wide simple dual-port mode. ECC allows you to detect and correct data errors in
the memory array. The M144K blocks have a single-error-correction
double-error-detection (SECDED) implementation. SECDED can detect and fix a
single bit error in a 64-bit word, or detect two bit errors in a 64-bit word. It cannot
detect three or more errors.
The M144K ECC status is communicated using a three-bit status flag
eccstatus[2..0]. The status flag can be either registered or unregistered. When
registered, it uses the same clock and asynchronous clear signals as the output
registers. When unregistered, it cannot be asynchronously cleared.
Table 3–3 lists the truth table for the ECC status flags.
Table 3–3. Truth Table for ECC Status Flags
Status
eccstatus[2]
No error
0
Single error and fixed
0
Double error and no fix
1
Illegal
0
Illegal
0
Illegal
1
Illegal
1
eccstatus[1]
0
1
0
0
1
0
1
eccstatus[0]
0
1
1
1
0
0
X
1 You cannot use the byte enable feature when ECC is engaged.
1 Read-during-write “old data mode” is not supported when ECC is engaged.
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation