EP4SE360F35I4 Datasheet, PDF (228/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–4
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
f For more information about which pins to use for memory clock pins, refer to the
External Memory Interface Handbook.
Figure 7–2. Memory Clock Generation
VCC
System Clock (3)
FPGA LEs I/O Elements
DQ
1
0
DQ
mem_clk (2)
mem_clk_n (2)
Notes to Figure 7–2:
(1) For pin location requirements,refer to the External Memory Interface Handbook.
(2) The mem_clk[0] and mem_clk_n[0] pins for DDR3, DDR2, and DDR SDRAM interfaces use the I/O input buffer for feedback required by
the ALTMEMPHY megafunction for tracking; therefore, use bidirectional I/O buffers for these pins. For memory interfaces using a differential DQS
input, the input feedback buffer is configured as differential input. For memory interfaces using a single-ended DQS input, the input buffer is
configured as a single-ended input. Using a single-ended input feedback buffer requires that I/O standard’s VREF voltage is provided to that I/O
bank’s VREF pins.
(3) To minimize jitter, regional clock networks are required for memory output clock generation.
Stratix IV devices offer differential input buffers for differential read-data strobe and
clock operations. In addition, Stratix IV devices also provide an independent DQS
logic block for each CQn pin for complementary read-data strobe and clock
operations. In the Stratix IV pin tables, the differential DQS pin pairs are denoted as
DQS and DQSn pins, while the complementary CQ signals are denoted as CQ and
CQn pins. DQSn and CQn pins are marked separately in the pin table. Each CQn pin
connects to a DQS logic block and the shifted CQn signals go to the negative-edge
input registers in the DQ IOE registers.
1 Use differential DQS signaling for DDR2 SDRAM interfaces running at or above
333 MHz.
DQ pins can be bidirectional signals, as in DDR3, DDR2, and DDR SDRAM, and
RLDRAM II common I/O (CIO) interfaces, or unidirectional signals, as in QDR II+,
QDR II SRAM, and RLDRAM II separate I/O (SIO) devices. Connect the
unidirectional read-data signals to Stratix IV DQ pins and the unidirectional
write-data signals to a different DQS/DQ group than the read DQS/DQ group.
Furthermore, the write clocks must be assigned to the DQS/DQSn pins associated to
this write DQS/DQ group. Do not use the CQ/CQn pin-pair for write clocks.
1 Using a DQS/DQ group for the write-data signals minimizes output skew, allows
access to the write-leveling circuitry (for DDR3 SDRAM interfaces), and allows
vertical migration. These pins also have access to deskewing circuitry (using
programmable delay chains) that can compensate for delay mismatch between signals
on the bus.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation