EP4SE360F35I4 Datasheet, PDF (127/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
5–11
PLL Clock Outputs
Stratix IV PLLs can drive both GCLK and RCLK networks, as described in Table 5–5
on page 5–13 and Table 5–6 on page 5–13.
Table 5–2 lists the connection between the dedicated clock input pins and GCLKs.
Table 5–2. Clock Input Pin Connectivity to the GCLK Networks
CLK (p/n Pins)
Clock Resources
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GCLK0
Y Y Y Y ————————————
GCLK1
Y Y Y Y ————————————
GCLK2
Y Y Y Y ————————————
GCLK3
Y Y Y Y ————————————
GCLK4
———— Y Y Y Y ————————
GCLK5
———— Y Y Y Y ————————
GCLK6
———— Y Y Y Y ————————
GCLK7
———— Y Y Y Y ————————
GCLK8
———————— Y Y Y Y ————
GCLK9
———————— Y Y Y Y ————
GCLK10
———————— Y Y Y Y ————
GCLK11
———————— Y Y Y Y ————
GCLK12
———————————— Y Y Y Y
GCLK13
———————————— Y Y Y Y
GCLK14
———————————— Y Y Y Y
GCLK15
———————————— Y Y Y Y
Table 5–3 lists the connectivity between the dedicated clock input pins and RCLKs in
Stratix IV devices. A given clock input pin can drive two adjacent RCLK networks to
create a dual-regional clock network.
Table 5–3. Clock Input Pin Connectivity to the RCLK Networks (Part 1 of 2)
Clock Resource
CLK (p/n Pins)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RCLK [0, 4, 6, 10]
RCLK [1, 5, 7, 11]
RCLK [2, 8]
RCLK [3, 9]
Y — — — — — — — — — — — — ———
— Y — — — — — — — — — — — ———
— — Y — — — — — — — — — — ———
— — — Y — — — — — — — — — ———
RCLK [13, 17, 21, 23, _{— — — — Y — — — — — — — — — — —}
27, 31]
RCLK [12, 16, 20, 22, _{— — — — — Y — — — — — — — — — —}
26, 30]
RCLK [15, 19, 25, 29] — — — — — — Y — — — — — — — — —
RCLK [14, 18, 24, 28] — — — — — — — Y — — — — — — — —
RCLK [35, 41]
— — — — — — — — Y — — — — ———
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1