EP4SE360F35I4 Datasheet, PDF (168/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–52
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Table 5–16. Dynamic Phase-Shifting Control Signals (Part 2 of 2)
Signal Name
SCANCLK
PHASEDONE
Description
Source
Destination
Free running clock from the core used
in combination with PHASESTEP to
enable and disable dynamic phase
shifting. Shared with SCANCLK for
dynamic reconfiguration.
GCLK, RCLK or I/O pin
PLL reconfiguration circuit
When asserted, this indicates to
core-logic that the phase adjustment is
complete and the PLL is ready to act
on a possible second adjustment
pulse. Asserts based on internal PLL
timing. De-asserts on the rising edge
of SCANCLK.
PLL reconfiguration
circuit
Logic array or I/O pins
Table 5–17 lists the PLL counter selection based on the corresponding
PHASECOUNTERSELECT setting.
Table 5–17. Phase Counter Select Mapping
PHASECOUNTERSELECT[3]
0
0
0
0
0
0
0
0
1
1
1
1
[2]
[1]
[0]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
Selects
All Output Counters
M Counter
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
C5 Counter
C6 Counter
C7 Counter
C8 Counter
C9 Counter
To perform one dynamic phase-shift, follow these steps:
1. Set PHASEUPDOWN and PHASECOUNTERSELECT as required.
2. Assert PHASESTEP for at least two SCANCLK cycles. Each PHASESTEP pulse enables
one phase shift.
3. Deassert PHASESTEP after PHASEDONE goes low.
4. Wait for PHASEDONE to go high.
5. Repeat steps 1-4 as many times as required to perform multiple phase-shifts.
The PHASEUPDOWN and PHASECOUNTERSELECT signals are synchronous to SCANCLK and
must meet tsu/th requirements with respect to SCANCLK edges.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation