EP4SE360F35I4 Datasheet, PDF (288/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–8
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS SERDES
LVDS SERDES
Figure 8–4 shows a transmitter and receiver block diagram for the LVDS SERDES
circuitry in the left and right banks. This diagram shows the interface signals of the
transmitter and receiver data path. For more information, refer to “Differential
Transmitter” on page 8–11 and “Differential Receiver” on page 8–17.
Figure 8–4. LVDS SERDES ⁽¹⁾, ⁽²⁾, ⁽³⁾
tx_in ¹⁰
Serializer ₂
IOE
DIN DOUT
IOE Supports SDR, DDR, or
Non-Registered Datapath
+
tx_out
-
tx_coreclock
10
rx_out
FPGA
Fabric
3 ^{(LVDS_LOAD_EN, diffioclk,}
tx_coreclock)
IOE Supports SDR, DDR, or
Non-Registered Datapath
2
IOE
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
LVDS Transmitter
LVDS Receiver
Synchronizer
DOUT DIN
DPA Circuitry
Retimed
Data
DIN
DPA Clock
rx_in
+
-
diffioclk
2
(LOAD_EN, diffioclk)
Clock MUX
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
rx_divfwdclk
rx_outclock
3 _{(LVDS_LOAD_EN,}
LVDS_diffioclk,
rx_outclock
Left/Right PLL
8 Serial LVDS
Clock Phases
LVDS Clock Domain
DPA Clock Domain
rx_inclock/tx_inclock
Notes to Figure 8–4:
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, the two left
and right PLLs are required.
(2) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10 bits.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation