EP4SE360F35I4 Datasheet, PDF (164/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–48
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
The rselodd bit indicates an odd divide factor for the VCO output frequency along
with a 50% duty cycle. For example, if the post-scale divide factor is 3, the high- and
low-time count values could be set to 2 and 1, respectively, to achieve this division.
This implies a 67% - 33% duty cycle. If you need a 50% - 50% duty cycle, you can set
the rselodd control bit to 1 to achieve this duty cycle despite an odd division factor.
The PLL implements this duty cycle by transitioning the output clock from high to
low on a falling edge of the VCO output clock. When you set rselodd = 1, you
subtract 0.5 cycles from the high time and you add 0.5 cycles to the low time. For
example:
■ High-time count = 2 cycles
■ Low-time count = 1 cycle
■ rselodd = 1 effectively equals:
■ High-time count = 1.5 cycles
■ Low-time count = 1.5 cycles
■ Duty cycle = (1.5/3) % high-time count and (1.5/3) % low-time count
Scan Chain Description
The length of the scan chain varies for different Stratix IV PLLs. The top and bottom
PLLs have ten post-scale counters and a 234-bit scan chain, while the left and right
PLLs have seven post-scale counters and a 180-bit scan chain. Table 5–11 lists the
number of bits for each component of a Stratix IV PLL.
Table 5–11. Top and Bottom PLL Reprogramming Bits (Part 1 of 2)
Block Name
C9 ⁽²⁾
C8
C7
C6 ⁽³⁾
C5
C4
C3
C2
C1
C0
M
N
Charge Pump Current
VCO Post-Scale divider (K)
Number of Bits
Counter
16
16
16
16
16
16
16
16
16
16
16
16
0
1
Other ⁽¹⁾
2
2
2
2
2
2
2
2
2
2
2
2
3
0
Total
18
18
18
18
18
18
18
18
18
18
18
18
3
1
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation